Identification of Processor’s Architecture of Executable Code Based on Machine Learning. Part 1. Frequency Byte Model

M. .. Buinevich; K. .. Izrailov

Proceedings of Telecommunication Universities
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ISSN 1813-324X (Print)
ISSN 2712-8830 (Online)

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Buinevich M..., Izrailov K... Identification of Processor’s Architecture of Executable Code Based on Machine Learning. Part 1. Frequency Byte Model. Proceedings of Telecommunication Universities. 2020;6(1):77-85. (In Russ.) https://doi.org/10.31854/1813-324X-2020-6-1-77-85

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ISSN 1813-324X (Print)
ISSN 2712-8830 (Online)

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